A significant amount of power is consumed during a write operation of an MRAM cell in an MRAM device having an array of cells. The write operation consists of passing currents through conductive lines external, but in close proximity, to the MRAM magnetic element. The magnetic fields generated by these currents are required to be sufficient to switch the magnetic state of the free layer of the magnetic element.
Magnetic random access memory (MRAM) using magnetic tunneling junctions (MTJ) is a strong candidate to provide a dense (areas of 8-25f2 where f is the smallest feature size), fast (1-30 ns read/write speed) and non volatile storage solution for future memory applications. The MTJ utilizes at least 2 magnetic layers, that sandwich a thin dielectric insulating layer like alumina or magnesia, with one magnetic layer being pinned by an antiferromagnetic film. The magnetic vectors in the layers can be oriented to be parallel or antiparallel to each other. The top magnetic layer with switchable magnetic vector is referred to as the storage or free layer.
To protect data from erasure or thermal agitation, an in-plane uniaxial magnetic anisotropy is needed for the magnetic free layer to store data. The intersection of Word and Bit line currents programs the MTJs of MRAM cells. The magnitude of the magnetic field used to switch the magnetic vector is proportional to the magnitude of the currents through these conductors. To reduce power consumption, it is desirable to increase the field to current ratio of said conductors.
One conventional technique for increasing the field to current ratio is to provide a magnetic liner for the conductors. An example of this is illustrated in FIG. 1. Shown there is MTJ stack 11 that rests on bottom electrode 12 and is topped by capping layer/top electrode 13. Conductive bit line 14 is seen to be in contact with cap 13. The direction of line 14 is normal to the plane of the figure. Ferromagnetic cladding layers 15 surround the bit line on three sides and serve to increase the current induced magnetic switching field that is applied to magnetic elements sitting on top of a metal line containing such a cladding layer. Power consumption and chip size may thus be reduced as less current is needed to generate a given switching field; switching word line transistors can thus also be made smaller. This is important because, for small magnetic elements (about 0.1 micron), it is expected that the switching fields will need to increase, causing the switch transistors to consume a significant amount of chip area.
Ferromagnetic cladding layers are typically made by wrapping a ferromagnetic material around the metal line. The magnetization of the ferromagnetic material is along the long axis of the metal line, thus creating poles at both ends. It has been shown that at such poles the fringing field is of the order of 50 to 300 Gauss. The magnetic cells should thus be some distance from the line ends in order not to shift the switching point of the cells. A safe distance can be calculated to be several micrometers—such a distance results in significant limitations to the chip layout since the arrays in memory chips should be packed as densely as possible.
Depending on current direction, ferromagnetic cladding layers may also show a hysteresis effect. The fields for switching of the ferromagnetic cladding layer magnetization direction are normally much higher than the fields for magnetic elements. There can also be domain effects in a ferromagnetic cladding layer which allow a partially local switching of the ferromagnetic cladding layer when a current is passed through the line. This partial switching broadens the switching field distribution for the magnetic elements thereby significantly reducing the write margin. The fringing fields and hysteresis effects associated with a ferromagnetic cladding layer thus limit the use of the ferromagnetic cladding layer in a memory chip having tight element spacing and thousands of elements in a sub-array.
In order to overcome these problems, liners having super-paramagnetic properties have been reported. The cladding layer in this case comprises ferromagnetic particles with a non-exchange coupled microstructure where the size of the micro domains is so small that their energy content is close to or below kT (on the order of up to 5 times kT) so such films have super paramagnetic properties and essentially behave like a paramagnet with high susceptibility. So a cladding layer of these particles acts as a super-paramagnet.
Without an external magnetic field induced by the current, local magnetic moments cancel each other out (super paramagnetic effect); with an external magnetic field the local magnetic moments are aligned by the current induced field to give the desired field enhancement effect. Thus, when a super-paramagnetic material is used, no hysteresis effects and no fringing fields occur.
The super-paramagnetic films discussed above are made either from small ferromagnetic particles in a polymeric matrix, as a particle film, or evaporated multi-layer films made out of repeated layers of Terbium and ferromagnetic particles, or deposition of ferromagnetic nano-particles.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,943,038, U.S. Patent Applications 2005/0208681, 2005/0164413 (Meixner et al) disclose a cladding layer formed within a trench over a bit line. The cladding layer is flux-concentrating. No insulator is formed between the bit line and the cladding layer. U.S. Pat. No. 6,885,074, U.S. Patent Applications 2004/0099908, 2005/0158992 (Durlam et al) and U.S. Pat. No. 6,559,511 (Rizzo) describe cladding on the top and sides of bit lines.
U.S. Patent Application 2005/0026308 (Ingvarsson et al) shows a super-paramagnetic lining on the top and sides of a conductor. U.S. Patent Application 2005/0274997 (Gaidis et al) teaches a magnetic flux layer on the top and sides of the write line. U.S. Patent Application 2006/0083053 (Hosotani) shows a soft magnetic flux concentrating layer formed around the bit line.